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IOT7210
Low-Power CMOS IEEE 488 Controller Device
Features
* Completely meets IEEE Standard 488-1978: - SH1, source handshake - AH1, acceptor handshake - T5 or TE5, talker or extended talker - L3 or LE3, listener or extended listener - SR1, service request www..com - RL1, remote local - PP1 or PP2, parallel poll, remote, or local configuration - DC1, device clear - DT1, device trigger - C1-C5, controller, all functions * Programmable data transfer rate * 16 registers, 8 read/8 write * 2 address registers: detect MTA, MLA, MSA (my talk/my listen/my secondary addresses) and provide 2 device addresses * End-of-string (EOS) message automatic detection * Automatic (IEEE Standard 488-78) command processing and undefined command read capability * DMA-capable * Programmable bus transceiver I/O specification, Texas Instruments/ Motorola/Intel-compatible * 1 MHz to 8 MHz clock range * TTL-compatible * CMOS * +5V single power supply * 40-pin plastic DIP or 44-pin plastic TQFP * 8080/85/86-compatible The IOT7210 low-power CMOS intelligent IEEE 488 controller meets all the functional requirements for talkers, listeners, and controllers as specified by the IEEE Standard 488-1978. It completely duplicates the NEC PD7210's function and provides enhancements such as lower power consumption and increased speed. Fully compatible with most processor architectures, the IOT7210 requires only the addition of the bus driver/receiver components to implement any IEEE 488 interface. In its 40-pin plastic DIP package, the IOT7210 provides users with a drop-in replacement for the PD7210 and eliminates the need for either software or hardware modifications. It is also available in
NEW
The IOT7210 is an enhanced replacement for the NEC PD7210 IEEE 488 controller device a 44-pin, 1.27 mm thick plastic TQFP package for surface-mount applications. than one device to receive data at the same time, with the slowest device controlling the data rate. Other control lines perform a variety of functions, such as device addressing and interrupt generation. In addition to providing all the control and data lines necessary for IEEE 488 operation, the IOT7210 provides a flexible interface to the standard IEEE 488 transceivers. The IOT7210 implements all the functions (including timing) that are required to interface to the IEEE 488 bus and provides high-level bus protocol management, which frees the host processor for other tasks. By performing these functions in dedicated hardware, the IOT7210 ensures bus compatibility with other IEEE 488 devices. The IOT7210 is controlled by its 16 internal registers. To reduce CPU overhead, bus data bytes can be transferred to and from the IOT7210 using DMA. The IOT7210's DMA feature is generic enough that it can be used to interface to most processors and buses.
IOT7210 Operation on the IEEE 488 Bus
Since its introduction in the 1970s, the IEEE 488 standard has become the most popular means of interconnecting instruments and controllers. This highly sophisticated standard has been refined over the years to provide a great degree of flexibility, permitting it to meet most instrumentation requirements. The IEEE 488 bus uses a common set of data and control lines to interconnect up to 15 devices. The device's capabilities are classified as a combination of talker, listener, and/or controller. Devices that incorporate the IOT7210 can perform all three functions--talker, listener, and controller. Data is transferred on the IEEE 488 bus in a bit-parallel, byte-serial fashion over eight bidirectional data lines. A 3-wire handshake ensures synchronization of transmission and reception and allows more
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Pin Configurations
Pin No.
DIP
1 2
(TQFP)
(40) (41)
Symbol
T/R1 T/R2 CLK RESET T/R3 DRQ DACK
I/O
O O
Functions
Transmit/Receive Control. Input/output control signal for the IEEE 488 bus transceivers. Transmit/Receive Control. The values of TRM1and TRM0 of the address mode register control the functions of T/R2 and T/R3. Clock. 1 MHz to 8 MHz reference clock for generating the state change prohibit times T1, T6, T7, T8, specified in IEEE Standard 488-1978. Reset. Resets the IOT7210 to an idle state when high (active high). Transmit/Receive Control. See T/R2. DMA Request. Requests data transfer. Becomes low on input of DMA acknowledge signal DACK. DMA Acknowledge. Active low. Connects the data bus (D0 - D7) to the byte in or data out register of the IOT7210. Chip Select. Active low. Enables access to the register selected by RS0 - RS2 (read or write operation). Read. Active low. Places contents of read register specified RS0 - RS2 on D0 - D7 (computer bus). Write. Active low. Writes data on D0 - D7 into the write register specified by RS0 - RS2. Interrupt Request. Active high/low. Becomes active due to any 1 of 13 internal interrupt conditions (unmasked). Active state software configurable. Active high on chip reset. Data Bus. 8-bit bidirectional data bus for interface to the computer system. Ground. Register Select. Select one of eight read (write) registers during a read (write) operation. Interface Clear. IEEE 488 control line. Clears the interface functions. Remote Enable. IEEE 488 control line. Selects remote or local control of the devices. Attention. IEEE 488 control line. Indicates whether data on DIO lines is an interface message or device dependent message. Service Request. IEEE 488 control line. Requests the service from the controller. Data Input/Output. IEEE 488 8-bit bi-directional bus for transfer of message. Data Valid. IEEE 488 handshake line. Indicates that data on DIO lines is valid. Ready for Data. IEEE 488 handshake line. Indicates that device is ready for data. Data Accepted. IEEE 488 handshake line. Indicates completion of message reception. End or Identify. IEEE 488 control line. Indicates the end of multiple byte transfer sequence or signals a parallel poll in conjunction with ATN. +5V DC.
GND DAV NRFD NDAC EOI Vcc T/R1 T/R2 CLK RESET T/R3 34 35 36 37 38 39 40 41 42 43 44
IOT7210P
T/R1 T/R2 CLK RESET T/R DRQ DACK CS RD WR INT D D D D D D D D GND
0 1 2 3 4 5 6 7 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
Vcc EOI NDAC NRFD DAV DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 SRQ ATN REN IFC RS 2 RS RS
1 0
3 4 5 6 7
(42) (43) (44) (1) (2)
I I O O I
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8 9 10 11 12-19 20
(3) (4) (5) (6) (8-11, 13-16) (7, 17, 25, 34)
CS RD WR INT, INT D0 - D7 GND RS0 - RS2 IFC REN ATN SRQ DIO1 - DIO8 DAV NRFD NDAC EOI VCC
I I I O I/O
IOT7210T
GND DIO 8 DIO 7 DIO 6 DIO 5 DIO 4 DIO 3 DIO 2 DIO 1 ATN SRQ
21-23 (18-20) 24 25 26 27 (21) (22) (23) (24)
I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
33 32 31 30 29 28 27 26 25 24 23
22 21 20 19 18 17 16 15 14 13 12
REN IFC RS2 RS1 RS0 GND D7 D6 D5 D4 Vcc
28-35 (26-33) 36 37 38 39 40 (35) (36) (37) (38) (12, 39)
1 2 3 4 5 6 7 8 9 10 11
GND D0 D1 D2 DRQ DACK INT CS WR RD D3
2
Functional Block Diagram
Registers Data In D7 -D0 Command Pass Through Message Decoder DIO8 -DIO1
CS
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RS2-RS0 RD WR DRQ DACK Address Mode AH1 Address Status Read/Write Control Byte Out Interface Functions
SH1
T5/TE5 Address 0/1 L3/LE3 IEEE 488 Control
End-of-String
SR1
RL1 Interrupt Mask 1/2
PP1/PP2 T/R 3-T/R1
INT
Interrupt Status 1/2
DC1
DT1 Serial Poll C1
Parallel Poll
C2
C3 Aux A/B/E C4
Clock
Internal Counter Auxillary Command Decoder
C5
Reset
3
Electrical Characteristics
Absolute Maximum Ratings
Exposing the device to stresses above those listed here could cause permanent damage to the IOT7210. The device is not meant to be operated under conditions outside the limits described in this specification. Exposure to absolute maximum rating conditions for extended periods www..com may affect device reliability.
AC/DC Characteristics
AC Characteristics
TA = 0C to 70C; Vcc = 5V 10% Parameter EOI DIO EOI T/R1 EOI T/R1 ATN NDAC ATN T/R1 ATN T/R2 DAV DRQ DAV NRFD DAV NDAC DAV NDAC DAV NRFD RD NRFD NDAC DRQ NDAC DAV WR DIO NRFD WR DAV DAV Symbol tEODI tEOTI1 tEOTI2 tATN0 tATT1 tATT2 tDVRQ tDVNR1 tDVND1 tDVND2 tDVNR2 tRNR tNDRQ tNDDV tWDI tNRDV tWDV tTRIG tAR tRA tRR tAD tRD tDF tRV tAW tWA tWW tDW tWD tRV tAKRQ tAKD tDH 50 0 0 0 55 35 35 10 Min Max 35 20 25 35 30 30 25 30 40 45 35 30 25 25 30 30 550 +tSYNC Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions PPSS PPAS, ATN = True PPSS PPAS, ATN = True PPAS PPSS, ATN = False AIDS ANRS, LIDS TACS + SPAS TADS, CIDS TACS + SPAS TADS, CIDS ACRS ACDS, LACS ACRS ACDS ACRS ACDS AWNS AWNS ANRS AWNS ANRS ACRS ANRS ACRS LACS, DI register selected STRS SWNS SGNS, TACS STRS SWNS SGNS SGNS SDYS BO register selected SDYS STRS, T1 = True SGNS SDYS STRS BO register selected; RFD = True; N + fc = 8MHz; T1 (high speed) RS0 to RS2 CS
TA = 25C
Supply Voltage, Vcc Input Voltage, VI Output Voltage, Vo Operating Temperature, TOPR Storage Temperature, TSTG -0.3V to +7.0V -0.3V to Vcc +0.3V -0.3V to Vcc +0.3V 0C to +70C -55C to 125C
Capacitance
TA = 25C; VCC = GND = 0V
Symbol Min Max Unit
CIN COUT CI/O 15 15 15 pF pF pF
TRIG Pulse Width Address Setup to RD Address Hold from RD RD Pulse Width Data Delay from Address Data Delay from RD Output Float Delay from RD RD Recovery Time Address Setup to WR Address Hold from WR WR Pulse Width Data Setup to WR Data Hold from WR WR Recovery Time DRQ Delay from DACK Data Delay from DACK DACK hold time from WR
Test Conditions
F = 1 MHz All pins except pin under test tied to AC ground
0 50 0 0 55 10 0 50
25 35 5
DC Characteristics
TA = 0C to 70C; Vcc = 5V 10% Input Low Voltage (except RESET) Input High Voltage (except RESET) Input Low Voltage (RESET) Input High Voltage (RESET) Low-Level Output Voltage High-Level Output Voltage (except INT) High-Level Output Voltage (INT) Input Leakage Current Output Leakage Current Supply Current VIL VIH -0.3 +2.1 VOL VOH1 VOH2 IIL IOL ICC -0.3 +.08 +2.0 VCC +0.3 0.7 V VCC +0.3 V +0.4 +2.4 +2.4 +3.5 -1 -10 V V
V V V V A A mA IOH = 1mA IOH = 1mA IOH = 50 A VIN = 0V to VCC VOUT = 0 to VCC Outputs Open
+1 +10 2
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Timing Waveforms
CPU/DMA Read
CS, RS 2-RS 0 t RD
AD
t
t RA
RR
t
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D7 -D0
t RD High Impedance tAD t AKD DACK tAKRQ DRQ Valid
t
RV
DF
High Impedance
DMA Write Timing
DRQ
DACK
t DH WR
CPU Write Timing
CS, RS2-RS0 t AW WR t WW t RV t DW D7 -D0 t WD t WA
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Registers
Internal Registers
The IOT7210 has 16 registers: 8 read and 8 write.
Register Name Addressing
R R RW RC S S S R DS 210 Data In [0R] 000 1 00 www..com 1 [1R] 0 0 1 1 0 0 Interrupt Status Interrupt Status 2 [2R] 0 1 0 1 0 0 Serial Poll Status [3R] Address Status [4R] Command Pass Through [5R] Address 0 [6R] Address 1 [7R] Byte Out [0W] 011 1 00 100 1 00 DI7 CPT INT S8 CIC DI6 APT PEND DI5 DET S6 DI4 END REM S5 LPAS DI3 DEC CO S4 TPAS CPT3 DI2 ERR S3 LA CPT2 DI1 DO S2 TA CPT1 DI0 DI S1 MJMN CPT0
Thirteen factors can generate an interrupt from the IOT7210, each with its own status bit and mask bit.
Specification
The interrupt status bits are always set to 1 if the interrupt condition is met. The interrupt mask bits decide whether or not the INT bit and the interrupt pin will be active for that condition.
SRQI LOK ATN SPMS
LOKC REMC ADSC
Interrupt Status Bits
INT CPT APT DET END DEC ERR DO DI SRQI LOKC REMC ADSC CO LOK REM DMAO DMAI OR of All Unmasked Interrupt Status Bits Command Pass Through Address Pass Through Device Trigger End (END or EOS Message Received) Device Clear Error Data Out Data In Service Request Input Lockout Change Remote Change Address Status Change Command Output Lockout Remote/Local Enable/Disable DMA Out Enable/Disable DMA In
1 0 1 1 0 0 CPT7 CPT6 CPT5 CPT4 110 1 00 111 1 00 000 0 10 X EOI BO7 CPT 0 S8 ton ARS EC7 DT0 DT1 BO6 APT rsv DL0 DL1 BO5 DET S6
AD5-0 AD4-0 AD3-0 AD2-0 AD1-0 AD5-1 AD4-1 AD3-1 AD2-1 AD1-1 BO4 END S5 BO3 DEC CO S4 0 AD4 EC3 BO2 ERR S3 0 AD3 EC2 BO1 DO S2 BO0 DI S1
Interrupt Mask 1 [1W] 0 0 1 0 1 0 Interrupt Mask 2 [2W] 0 1 0 0 1 0 Serial Poll Mode [3W] Address Mode [4W] Auxiliary Mode [5W] Address 0/1 [6W] End of String [7W] 011 0 10 100 0 10 110 0 10 111 0 10
SRQI DMAO DMAI lon TRM1 TRM0 DT EC6 DL EC5 AD5 EC4
LOKC REMC ADSC ADM1 ADM0 AD2 EC1 AD1 EC0
1 0 1 0 1 0 CNT2 CNT1 CNT0 COM4 COM3 COM2 COM1 COM0
Noninterrupt Related Bits
Data Registers
The data registers are used for data and command transfers between the IEEE 488 and the computer. The Data In register holds data sent from the IEEE 488 to the computer; the Byte Out register holds information written into it for transfer to the IEEE 488 bus.
Interrupt Registers
The interrupt registers consist of interrupt status bits, interrupt mask bits, and some other non-interrupt bits.
Read
Interrupt Status 1 [1R]
CPT APT DET END DEC ERR DO DI
Serial Poll Registers
The serial poll mode register holds the STB (status byte: S8, S6-S1) sent over the IEEE 488 bus and the local message rsv (request service). The serial poll mode register may be read through the serial poll status register. The PEND is set by rsv = 1 and cleared by NPRS*rsv = 1 (NPRS = negative poll response state).
Data In [0R]
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
INT
Interrupt Status 2 [2R]
SRQI LOK REM CO LOKC REMC ADSC
Byte Out [0W]
BO7 BO6 BO5 BO4 BO3 BO2 BO1 BO0
Write
Interrupt Mask 1 [1W]
CPT APT DET END DEC ERR DO DI
Read
Serial Poll Status [3R]
S8 PEND S6 S5 S4 S3 S2 S1
Interrupt Mask 2 [2W]
0 SRQI DMAO DMAI CO LOKC REMC ADSC
Write
Serial Poll Mode [3W]
S8 rsv S6 S5 S4 S3 S2 S1
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Registers
Address Status/Address Mode Registers
The address mode register selects the address mode of the device and also sets the mode for the transceiver control lines, T/R3 and T/R2.
Address Modes ton lon ADM1 ADM0
1 0 0 0
Address Mode
Talk only mode Listen only mode Address mode 11
Contents of Address 0 Register
Contents of Address 1 Register
Address identification necessary (no controller on the IEEE 488 bus) Not used Major talk address or major listen address Primary address (talk or listen) Primary address (major talk or major listen) Minor talk address or minor listen address Secondary address (talk or listen) Primary address (minor talk or minor listen)
Address Status [4R]
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LA TA MJMN
0 0
1 0
0 0
0 1
Address Mode [4W]
ton lon TRM1 TRM0 0 0 AMD1 ADM0
0 The TRM1 and TRM0 values of the address mode register determine the functions of the T/R2 and T/R3 pins.
0
1
0
Address mode 22 Address mode 33
0
0
1
1
T/R2
EOIOE CIC CIC CIC
T/R3
TRIG TRIG EOIOE PE
TRM1
0 0 1 1
TRM0
0 1 0 1
Notes: Combinations other than those indicated are prohibited. 1 Either MTA or MLA reception is indicated by coincidence of either address with the received address; interface function T or L 2 Address register 0 = primary: address register 1 = secondary; interface function TE or LE 3 CPU must read secondary address via Command Pass Through register; interface function (TE or LE)
EOIOE = TACS + SPAS + CIC * CSBS EOI pin output enable. When 1: output When 0: input CIC = CIDS + CADS Controller in charge. When 1: ATN = output, SRQ = input When 0: ATN = input, SRQ = output PE = CIC + PPAS Pull-up enable for DIO8 - DIO1 and DAV lines. When 1: Three-state When 0: Open-collector TRIG Pulses high when DTAS state is initiated or when a trigger auxiliary command is issued. Upon reset, TRM0 and TRM1 become 0 (TRM0 = TRM1 = 0) so that T/R2 and T/R3 both become low.
Address Registers
The IOT7210 is able to automatically detect two addresses that are held in address registers 0 and 1, as specified by the address mode register.
Command Pass Through Register
The CPT register enables the CPU to read the DIO lines in the cases of undefined command, secondary address, or parallel poll response.
Address 0 [6R]
X DT0 DL0 AD5-0 AD4-0 AD3-0 AD2-0 AD1-0
Command Pass Through [5R]
CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 CPT0
Address 1 [7R]
EOI DT1 DL1 AD5-1 AD4-1 AD3-1 AD2-1 AD1-1
Address 0/1 [6W]
ARS DT DL AD5 AD4 AD3 AD2 AD1
Address Status Bits
Data Transfer Cycle (Device in CSBS) LPAS Listener Primary Addressed State TPAS Talker Primary Addressed State CIC Controller Active LA Listener Addressed TA Talker Addressed MJMN Set = Minor T/L Address, Reset = Major T/L Address SPMS Serial Poll Mode State ATN
The addresses are set by writing into the address 0/1 register.
Address 0/1 Register Bit Selections
ARS Selects either address register 0 or 1 DT Permits or prohibits address to be detected as Talk DL Permits or prohibits address to be detected as Listen AD5-AD1 Device address value EOI Holds the value of EOI line when data is received
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Registers
End of String Register
This register holds either a 7- or 8- bit EOS message byte used in the IEEE 488 system to detect the end of a data block. Auxiliary Mode register A controls the specific use of this register.
Auxiliary Commands
Auxiliary Commands
0 0 0 C4 C3 C2 C1 C0
Auxiliary A Register
Of the 5 bits that may be specified as part of its access word, two bits control the IEEE 488 data receiving modes of the IOT7210 and 3 bits control how the EOS message is used.
End of String [7W]
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EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0
Command Aux C4 C3 C2 C1 C0 Comm
00000 00010 iepon crst rrfd trig rtl seoi nvld vld sppf gts tca tcs tcse ltn ltnc lun epp sifc sren dsc
Function
Immediate Execute pon, Generate Local pon message Chip Reset (Same as External Reset) Release RFD Trigger Return to Local Send EOI message Nonvalid (OSA Reception), Release DAC Holdoff Valid (MSA Reception, CPT, DEC, DET), Release DAC Holdoff Set/Reset Parallel Poll Flag Go To Standby Take Control Asynchronously Take Control Synchronously Take Control Synchronously on End Listen Listen with Continuous Mode Local Unlisten Execute Parallel Poll Set/Reset IFC Set/Reset REN Disable System Control
Auxiliary A Register
1 0 0 A4 A3 A2 A1 A0
Auxiliary Mode Register
This is a multipurpose register.
Auxiliary Mode [5W]
CNT2 CNT1 CNT0 COM4 C0M3 COM2 COM1 COM0
0 0 0 0 0
0 0 0 0 0
0 1 1 1 1
1 0 0 1 1
1 0 1 0 1
A1
0 0 1 1
A0
0 1 0 1
Data Receiving Mode
Normal Handshake Mode RFD Holdoff on All Data Modes RFD Holdoff on End Mode Continuous Mode
A write to this register generates one of the following operations according to the values of the CNT bits.
CNT COM Function
01111 0X001 10000 10001 10010 11010 10011 11011 1 1 1 1 1 1 1 X X 0 1 1 1 1 1 0 0 1 1 0 0 1 0 1 0
Permits (prohibits) the A2 0 Prohibit setting of the END bit by 1 Permit reception of the EOS message Permits (prohibits) automatic transmission 0 Prohibit of END message simul1 Permit taneously with the transmission of EOS message (TACS)
210 4 3 2 1 0 0 0 0 C4 C3 C2 C1 C0 Issues an auxiliary command specified by C4 to C0 0 0 1 0 F3 F2 F1 F0 The reference clock frequency determines T1, T6, T7, & T9 0 1 1 U S P3 P2 P1 Sets the parallel poll register 1 0 0 A4 A3 A2 A1 A0 Sets the auxiliary A register 1 0 1 B4 B3 B2 B1 B0 Sets the auxiliary B register 1 1 0 0 0 0 E1 E0 Sets the auxiliary E register
A3
Makes the 8 bits (7 bits) A1 0 7-bit EOS of the EOS register the 0 8-bit EOS valid EOS message
Internal Counter
The internal counter generates the state change prohibit times (T1, T6, T7, T9) specified in the IEEE Standard 488-1978 with reference to the clock frequency. F3-F0 specify the clock frequency from 1 to 8 MHz.
Internal Counter
0 0 1 0 F3 F2 F1 F0
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Registers
Auxiliary B Register
The auxiliary B register is much like the A register in that it controls the special operating features of the device.
Auxiliary E Register
The register controls the IOT7210's Data Acceptance modes.
Auxiliary E Register
1 1 0 0 0 0 E1 E0
Auxiliary B Register
1 0 1 B4 B3 B2 B1 B0
Permits (prohibits) the w w w . D aB a S1h Permit U . c o m of the CPT bit on t e e t 4 setting 0 0 Prohibit receipt of an undefined command B1 1 Permit 0 Prohibit Permits (prohibits) the transmission of the END message when in serial poll active state (SPAS) T1 in source handshake function after transmission of second byte following data transmission
E0 1 0 E1 1 0
Enable DAC holdoff by initiation Disable of DCAS Enable DAC holdoff by initiation Disable of DTAS
Parallel Poll Register
The Parallel Poll register defines the IOT7210's parallel poll response.
1 T1 (highspeed) B2
Parallel Poll Register
0 1 1 U S P3 P2 P1
1 T1 (low- Sets T in all cases 1 speed) B3 1 0 INT INT Specifies the active level of the INT pin SRQS indicates the value of the ist level local message (the value of the parallel poll flag is ignored) SRQS = 1...ist = 1 SRQS = 0...ist = 0 B4 0 ist = The value of the parallel Parallel poll flag is taken as the ist Poll Flag local message
U S P3 P2 P1
1 = No Parallel Poll Response 0 = Parallel Poll Response Specify Status Bit Polarity 1 = In Phase 0 = Reverse Phase
1 ist = SRQS
Specify Status Bit Output Line (DIO1-DIO8)
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IEEE 488 Transceiver Examples
Low-Speed
IOT7210 DIO8 DIO7 DIO6 MC3448AX4 Data A Data B Data C Data D S/RA-S/R D Bus A Bus B Bus C Bus D PEA-PE D GPIB DIO8 DIO7 DIO6 DIO5
High-Speed
IOT7210 DIO8 DIO7 DIO6 DIO5 DIO4 D8 D7 D6 D5 D4 D3 D2 D1 PE TE IEEE 488 Bus TE SN75160 B8 B7 B6 B5 B4 B3 B2 B1
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DIO4 DIO3 DIO2 DIO1 T/R 1 T/R 3 (EOIOE) EOI DAV NRFD NDAC
Data A Data B Data C Data D S/RA-S/R D
Bus A Bus B Bus C Bus D PEA-PE D
DIO4 DIO3 DIO2 DIO1
DIO3 DIO2 DIO1 T/R 3 (PE)
S/RA Data A S/RB Data B S/RC Data C S/RD Data D
Bus A Bus B Bus C Bus D PEA -PE D
EOI DAV NRFD
T/R 1
T/R 2 (CIC) SRQ
DC SRQ ATN EOI
NDAC
ATN EOI
T/R 2 (CIC) SRQ ATN REN IFC
S/RA Data A S/RB Data B S/RC Data C S/RD Data D
SN75161
Bus A Bus B Bus C Bus D PEA -PE D SRQ ATN REN IFC
DAV NRFD NDAC IFC REN
DAV NRFD NDAC IFC REN
HL
L
In this example, a high-speed data transfer cannot be made since the bus transceiver is of the open-collector type (set B2 = 0)
In the case of low-speed data transfer (B2 = 0), the TR3 pin can be used as a TRIG output; the PE input of SN75160 should be cleared to 0
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Package Outlines
Package Outline for IOT7210P
Item Millimeters
A B C D www..com E F G H I J K L 51.94-52.71 1.90-2.42 2.54 BSC 0.38-0.56 1.14-1.66 3.04-3.56 0.38-1.15 3.68-3.94 4.19-5.59 15.24-15.88 13.46-14.10 0.20-0.36
A G B E C D
H I F L
J K
0-15
Side View
Package Outline for IOT7210T
D D/2 D/2 D1
33 23
Millimeter Symbol Min Nom Max
A A1 A2 D D/2 D1 E E/2 E1 L e b c 0.05 0.95 0.10 1.00 12.00 BSC 6.00 BSC 10.00 BSC 12.00 BSC 6.00 BSC 10.00 BSC 0.60 0.80 BSC 0.37 1.27 0.15 1.12 E E/2 E/2
34
22
E1 Index
44 12
0.45 0.30 0.09
0.75 0.45 0.18 A A1 A2
1 e
b
11
11-13
c
See Detail
0.13 R min
0.20 min 0 min 0.13/0.20 R L
1.00
11-13
0-7
Detail
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Ordering Information
Ordering Information
Description Low-power CMOS IEEE 488 controller device in a 40-pin plastic DIP Low-power CMOS IEEE 488 controller device in a 44-pin plastic TQFP Part No. IOT7210P IOT7210T
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Printed in the U.S.A.
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